SPC5644AF0MMG1 test report

Date：2021-09-15 16:06:33Views：867Author：CHUANGXIN ONLINE TESTING LAB

Device Description:

The MPC5644A has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM and 4 MB of internal flash memory. The MPC5644A includes an external bus interface, and also a calibration bus that is only accessible when using the Freescale VertiCal Calibration System.