Exploring IC chip aging tests and their effects

Date：2024-01-23 15:48:33Views：65

IC chip aging test refers to long-term stability testing of integrated circuit chips under specific conditions to verify their reliability and stability within their service life. Its main function is to evaluate the lifespan and performance of chips, in order to improve their quality and reliability.

The most advanced type of aging is TDBI (testing during burn in aging). Full functional testing mode and full response monitoring are used for each individual chip. The advantage is that it can determine accurate fault time and characteristics, as well as equipment or contact issues. Minimize aging leakage to the greatest extent possible and recycle chips that have not been exposed to aging voltage. The individual monitoring of each chip limits the number of components that can be subjected to pressure on an aging board, and the required equipment makes this type of aging typically very expensive.

Aging tests are mainly divided into four categories:

1、 High temperature working life (HTOL):

The reliability of a product is determined by accelerating the thermal activation failure mechanism. Under deviant operating conditions, customer parts may be affected by high temperatures. Under pressure, dynamic signals are usually applied to the equipment. Typical Vcc is the maximum operating voltage. This experiment is used to predict long-term failure rates. All test samples must pass the final electrical test before HTOL testing. Applicable specifications: JESD22-A108, MIL-STD-883, EIAJ-ED4701-D323.

2、 HTSL testing:

Measurement equipment has resistance to high temperature environments that simulate storage environments. The stress temperature is usually set at 1255 ° C or 150 ° C to accelerate the effect of temperature on the specimen. During testing, no bias voltage was applied to the device. Applicable specifications: JESD22-A103, MIL-STD-883

3、 HAST testing:

The high temperature and humidity accelerated stress test (HAST) accelerated the same failure mechanism as the 85 ° C/85% relative humidity test. The typical testing conditions are 130 ° C pressurized and non condensing/85% relative humidity. Protect the material (packaging or sealing) or metal conductor through the interface between the external protective material and the metal conductor through the external protective material department. Before conducting high acceleration temperature and humidity stress tests, the samples of surface mounted devices are subjected to pre-treatment and final electrical testing. Applicable specifications: JESD22-A110 (biased), JESD22-A118 (unbiased).

4、 CSP reliability testing:

In order to adapt to thinner, smaller, and lower power consumption products, reliability assessment, system miniaturization, especially in the consumer electronics market, are driving the development of advanced packaging technology. This increases the size of chip level packaging (CSP), which is essentially the same as the chip. CSP's substrate is becoming thinner to support the electronic devices they enter. Unfortunately, this attractive size advantage of CSP becomes fragile and fragile during the processing. Due to handling or insertion, this may lead to rupture, cracking, and ball damage.

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